Communications links, due to distance, are normally specified as synchronous or plesiochronos in nature, and in the presence of link errors or faults, may receive input streams at completely uncontrolled signaling rates. Examples of such communication links include SONET, OTN, Fibre Channel, Ethernet, InfiniBand, Serial ATA, SAS (serial attached SCSI), and some forms of PCI Express. Some of these links may be configured to transmit using a recovered clock (e.g., SONET), though most transmit using a local reference clock so as to limit any jitter transfer from a recovered clock.
All of these interfaces specify maximum allowed tolerance of the local reference clock, or maximum offset between the reference clock at the transmitting and receiving ends of a link. For SONET links this offset is normally specified as low as 20 ppm, while for Fibre Channel it can be as high as +/−100 ppm.
The logic that processes received data needs to process at least some portion of the data in the recovered clock domain. This logic is normally designed to operate over the normal or “operating” range of the system signaling rate, plus some small margin. However, in the case of a fiber break or similar fault, the receiver in the communication system may start processing noise as if it were data. When the receive phase locked loop (PLL) attempts to track the uncontrolled transitions in this noise, it can speed up to much faster than the normal operating range of the system. Typical voltage controller oscillators (VCOs) can operate at 2× or faster than their target operating frequency. If the downstream data-processing logic were presented with a clock this far out of specification, the logic would suffer multiple errors due to setup and hold violations.
To prevent this from happening, range-control hardware is added to the clock recovery hardware to limit the range of operation of the recovered clock to that which the downstream logic can tolerate. When an out-of-specification data stream is detected, the clock recovery circuit is directed to ignore the received data, and instead lock onto a local controlled signal that is within the allowed range of operation.
For these range-control circuits to work, they need to be able to respond to all of the potential link-fault conditions before the recovered clock presents an out of specification clock to the downstream logic. Likewise, it must also detect and report variations in link signaling rate that do not cause a permanent out-of-specification clock, but do present an invalid clock for a short period. However, tradeoffs in PLL bandwidth vs. phase noise are often necessary that allow the VCO to move faster than the evaluation period needed to ensure proper operating range. This leaves the user with a “hole” where, when presented with some types of external conditions, the normal range-control logic cannot detect the out-of-spec condition until the system is substantially out of specification, if at all.